1. Field of the Invention
The present invention relates to an apparatus for reading data from a memory and particularly to a read data clock signal generation circuit for generating a read data clock signal to read the data. The present invention can shorten a read cycle time for the data, and thus can raise the throughput of a computer system.
2. Description of the Related Art
In the computer system, as is well known, data stored in a memory (RAM) is read in response to an address signal and a chip selection signal transmitted from a central processing unit (CPU). In this case, the arrival of these signals at the RAM is delayed due to the length of the wiring pattern between the CPU and the RAM on the printed circuit board. Further, output of the read data is also delayed for a certain access time due to a transmission delay time within each RAM. In this case, it is difficult to shorten the transmission delay time caused for the above reasons because of the structural factor when designing a large scale integrated circuit (LSI). Therefore, for the same reasons, it is also difficult to shorten the read cycle time for improving the throughput of the computer system by reducing the transmission delay time. However, it is relatively easy to shorten the read cycle time by reducing a number of clock cycles between address sending and receiving data, but in this case, a problem occurs regarding the timing between the clock signal and the read data clock signal when the computer system has a single clock mode for diagnostic purposes. This problem is explained in detail hereinafter.